1. Field of the Invention
The present invention relates to parallel/serial conversion circuit for converting parallel data to serial data, and a serial data generation circuit, a synchronization signal generation circuit, a clock signal generation circuit, a serial data transmission device, a serial data reception device, and a serial data transmission system. The parallel/serial conversion circuit may comprise a CMOS logic circuit. The parallel/serial conversion circuit may be used as a serial data transmission output circuit in an integrated circuit (e.g., a microprocessor, a digital signal processor, and the like).
2. Description of the Related Art
A serial data transmission device comprises a parallel/serial conversion circuit. The parallel/serial conversion circuit comprises a shift register. Parallel data containing a plurality of bits is written into the shift register. A shift clock signal is input to the shift register. The shift register shifts the parallel data containing a plurality of bits in response to the input shift clock signal. The plurality of bits are shifted on a bit-by-bit basis so that a signal indicating each bit is serially output from the shift register, resulting in serial data containing the plurality of bits. A serial data signal indicating the serial data is input to a serial data reception device.
A serial data transmission system comprises a serial data transmission device, a serial data reception device, two transmission paths connecting the serial data transmission device and the serial data reception device. One of the transmission paths is used to transmit a serial data signal from the serial data transmission device to the serial data reception device. The other transmission path is used to transmit a signal for separating one bit from another in a plurality of bits contained in serial data signal, from the serial data transmission device to the serial data reception device.
A signal for separating one bit from another bit in a plurality of bits contained serial data, includes other signals in addition to a shift clock signal.
Japanese Laid-Open Publication No. 10-322404 discloses a serial data transmission method which uses a signal for separating one bit from another bit in a plurality of bits contained serial data, other than a shift clock signal.
FIG. 7 shows signal waveforms for explaining a serial data transmission method as disclosed in Japanese Laid-Open Publication No. 10-322404.
This serial data transmission method uses a serial data transmission system which comprises a serial data transmission device, a serial data reception device, and two transmission paths connecting the serial data transmission device and the serial data reception device. One of the two transmission paths (first transmission path) is used to transmit a serial data signal 200 from the serial data transmission device to the serial data reception device. The other transmission path (second transmission path) is used to transmit a separation signal 201 from the serial data transmission device to the serial data reception device. Serial data indicated by the serial data signal 200 contains a plurality of bits. The separation signal 201 is used to separate one bit from another in a plurality of bits contained in the serial data.
The serial data transmission device transmits the serial data signal 200 from the serial data transmission device to the serial data reception device via the first transmission path. A signal indicating each bit contained in serial data is transmitted as a sequence of logic values xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 where two different voltage levels of the signal indicate the respective logic values. When two bits having the same logic value are consecutively output as the serial data signal 200 from the serial data transmission device, the serial data transmission device transmits a separation signal 201 having a predetermined voltage level from the serial data transmission device to the serial data reception device via the second transmission path.
However, conventional serial data transmission systems have the following problems.
(1) Conventional parallel/serial conversion circuits require a clock generation circuit, a clock division circuit, and the like. This is because it is necessary to process a shift clock signal for generating serial data externally input to a parallel/serial conversion circuit. Therefore, the size of conventional parallel/serial conversion circuits is inevitably large.
(2) Conventional parallel/serial conversion circuits results in wasted power consumption. This is because no matter whether or not the conventional parallel/serial conversion circuit performs parallel/serial conversion, the clock generation circuit, the clock division circuit, and the like are operated due to the shift clock signal externally supplied to the parallel/serial conversion circuit.
When a conventional parallel/serial conversion circuit does not perform parallel/serial conversion, the supply of a shift clock signal may not be stopped so as to reduce wasted power consumption. However, such a conventional parallel/serial conversion circuit requires a control circuit for stopping the external supply of a shift clock signal. Therefore, the size of the conventional parallel/serial conversion circuit is inevitably increased.
(3) Conventional serial data transmission systems require a transmission path for transmitting a signal for separating one bit from another in a plurality of bits contained in serial data. This is because a serial data reception device converts a serial data signal to a parallel data signal.
According to an aspect of the present invention, a parallel/serial conversion circuit is provided, which comprises: a parallel/serial conversion section for converting first parallel data to first serial data and converting second parallel data to second serial data; and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal. The parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal. A combination of the first serial data and the second serial data indicates bit separation, a logic value xe2x80x980xe2x80x99, or a logic value xe2x80x981xe2x80x99. The shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data.
In one embodiment of this invention, the parallel/serial conversion section may comprise a first shift register, a second shift register, a first pulse generation circuit, and a second pulse generation circuit. The first and second parallel data may each contain a plurality of bits. The first serial data and second serial data may be inverse to each other in terms of the bit value. The first shift register may shift the first parallel data stored therein on a bit-by-bit basis in response to the shift clock signal to convert the first parallel data to third serial data. The second shift register may shift the second parallel data stored therein on a bit-by-bit basis in response to the shift clock signal to convert the second parallel data to fourth serial data. The first pulse generation circuit may receive the third serial data and converts the third serial data to the first serial data based on each bit contained in the third serial data. The second pulse generation circuit may receive the fourth serial data and converts the fourth serial data to the second serial data based on each bit contained in the fourth serial data.
In one embodiment of this invention, a signal indicating the first serial data may contain a first end data signal indicating an end of the first serial data, and a signal indicating the second serial data may contain a second end data signal indicating an end of the second serial data.
In one embodiment of this invention, the parallel/serial conversion circuit further may comprise a delay circuit for determining a delay time of the shift clock signal.
According to another aspect of the present invention, a serial data generation circuit for generating serial data containing a plurality of bits is provided, which comprises: a serial data generation section for combining first serial data and second serial data generated by a parallel/serial conversion circuit to generate the serial data. A serial data signal indicating the serial data includes a signal for separating one bit from another in the plurality of bits contained in the serial data. The parallel/serial conversion circuit comprises: a parallel/serial conversion section for generating the first serial data by converting first parallel data to the first serial data and generating the second serial data by converting second parallel data to the second serial data; and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal. The parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal. A combination of the first serial data and the second serial data indicates bit separation, a logic value xe2x80x980xe2x80x99, or a logic value xe2x80x981xe2x80x99. The shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data.
According to another aspect of the present invention, a synchronization signal generation circuit for generating a synchronization signal indicating an end of serial data is provided, in which the serial data is generated by combining first serial data and second serial data generated by a parallel/serial conversion circuit. The synchronization signal generation circuit comprises: a synchronization signal generation section for generating the synchronization signal based on a combination of a first end data signal contained in a signal indicating the first serial data and a second end data signal contained in a signal indicating the second serial data. The first end data signal indicates an end of the first serial data and the second end data signal indicates an end of the second serial data. The parallel/serial conversion circuit comprises: a parallel/serial conversion section for generating the first serial data by converting first parallel data to the first serial data and generating the second serial data by converting second parallel data to the second serial data; and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal. The parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal. A combination of the first serial data and the second serial data indicates bit separation, a logic value xe2x80x980xe2x80x99, or a logic value xe2x80x981xe2x80x99. The shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data.
According to another aspect of the present invention, a clock signal generation circuit for generating a clock signal is provided, in which the clock signal separates one bit from another in a plurality of bits contained in serial data, and the serial data is generated by combining first serial data and second serial data generated by a parallel/serial conversion circuit. The clock signal generation circuit comprising: a clock signal generation section for generating the clock signal based on a combination of a first pulse signal contained in a signal indicating the first serial data and a second pulse signal contained in a signal indicating the second serial data. The first pulse signal and the second pulse signal separate one bit from another in a plurality of bits contained in the serial data. The parallel/serial conversion circuit comprises: a parallel/serial conversion section for generating the first serial data by converting first parallel data to the first serial data and generating the second serial data by converting second parallel data to the second serial data; and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal. The parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal. A combination of the first serial data and the second serial data indicates bit separation, a logic value xe2x80x980xe2x80x99, or a logic value xe2x80x981xe2x80x99. The shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data.
According to another aspect of the present invention, a serial data transmission device is provided, which comprises a parallel/serial conversion circuit comprising a parallel/serial conversion section for converting first parallel data to first serial data and converting second parallel data to second serial data; and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal. The parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal. A combination of the first serial data and the second serial data indicates bit separation, a logic value xe2x80x980xe2x80x99, or a logic value xe2x80x981xe2x80x99. The shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data.
According to another aspect of the present invention, a serial data reception device is provided, which comprises: a serial data generation circuit for generating serial data containing a plurality of bits; a synchronization signal generation circuit for generating a synchronization signal indicating an end of the serial data; and a clock signal generation circuit for generating a clock signal. The serial data generation circuit generates the serial data by combining the first serial data and the second serial data generated by a parallel/serial conversion circuit. A serial data signal indicating the serial data includes a bit separation signal separating one bit from another in the plurality of bits contained in the serial data. The synchronization signal generation circuit generates the synchronization signal based on a combination of the first end data signal contained in a signal indicating the first serial data and a second end data signal contained in a signal indicating the second serial data. The first end data signal indicates an end of the first serial data and the second end data signal indicates an end of the second serial data. The clock signal generation circuit generates the clock signal based on a combination of a first pulse signal contained in the signal indicating the first serial data and a second pulse signal contained in the signal indicating the second serial data. The clock signal separates one bit from another in the plurality of bits contained in the serial data. The first pulse signal and the second pulse signal separate one bit from another in a plurality of bits contained in the serial data. The parallel/serial conversion circuit comprises: a parallel/serial conversion section for generating the first serial data by converting first parallel data to the first serial data and generating the second serial data by converting second parallel data to the second serial data; and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal. The parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal. A combination of the first serial data and the second serial data indicates bit separation, a logic value xe2x80x980xe2x80x99, or a logic value xe2x80x981xe2x80x99. The shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data.
According to another aspect of the present invention, a serial data transmission system is provided, which comprises: a serial data transmission device comprising a parallel/serial conversion circuit for generating first serial data and second serial data; a serial data reception device for receiving the first serial data and the second serial data; a first transmission path for transmitting the first serial data from the serial data transmission device to the serial data reception device; and a second transmission path for transmitting the second serial data from the serial data reception device to the serial data transmission device. The parallel/serial conversion circuit comprises: a parallel/serial conversion section for generating the first serial data by converting first parallel data to the first serial data and generating the second serial data by converting second parallel data to the second serial data; and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal, the parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal, a combination of the first serial data and the second serial data indicates bit separation, a logic value xe2x80x980xe2x80x99, or a logic value xe2x80x981xe2x80x99, and the shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data. The serial data reception device comprises a serial data generation circuit for generating serial data containing a plurality of bits, a synchronization signal generation circuit for generating a synchronization signal indicating an end of the serial data, and a clock signal generation circuit for generating a clock signal. The serial data generation circuit generates the serial data by combining the first serial data and the second serial data. A serial data signal indicating the serial data includes a bit separation signal separating one bit from another in the plurality of bits contained in the serial data. The synchronization signal generation circuit generates the synchronization signal based on a combination of the first end data signal contained in a signal indicating a first serial data and a second end data signal contained in a signal indicating the second serial data. The first end data signal indicates an end of the first serial data and the second end data signal indicates an end of the second serial data. The clock signal generation circuit generates the clock signal based on a combination of a first pulse signal contained in the signal indicating the first serial data and a second pulse signal contained in the signal indicating the second serial data. The clock signal separates one bit from another in the plurality of bits contained in the serial data. The first pulse signal separates and the second pulse signal separate one bit from another in a plurality of bits contained in the serial data.
Hereinafter, functions of the present invention will be described.
The parallel/serial conversion circuit of the present invention combines first serial data and second serial data, a combination of which indicates bit separation, a logic value xe2x80x980xe2x80x99, or a logic value xe2x80x981xe2x80x99, to generate a shift clock signal. The parallel/serial conversion circuit of the present invention shifts the first parallel data in response to the generated shift clock signal, thereby converting the first parallel data to first serial data. Also, the parallel/serial conversion circuit of the present invention shifts the second parallel data in response to the generated shift clock signal, thereby converting the second parallel data to second serial data.
As a result, the parallel/serial conversion circuit of the present invention can generate a shift clock signal by itself and convert parallel data to serial data in response to the generated shift clock signal.
According to the serial data reception device of the present invention, a synchronization signal and a clock signal can be generated based on a positive transmission data signal and a negative transmission data signal. Therefore, for example, serial data can be input serially into a shift register in response to the clock signal, thereby making it possible to output parallel data in response to the synchronization signal.
Thus, the invention described herein makes possible the advantages of a providing parallel/serial conversion circuit, a serial data generation circuit, a synchronization signal generation circuit, a clock signal generation circuit, a serial data transmission device, a serial data reception device, and a serial data transmission system, which (1) can produce a shift clock signal without a clock generation circuit, a clock division circuit, and the like, (2) can reduce power consumption when parallel/serial conversion is not performed, and (3) can transmit serial data without a transmission path for transmitting a signal for separating one bit from another in a plurality of bits in the serial data.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.